1/7 ? semiconductor MSM6778 general description the MSM6778 is a dot-matrix lcd common driver. fabricated in cmos technology, the device contains two 60-bit bidirectional shift registers, two 60-bit level shifters, and two 60-bit 4-level drivers. the MSM6778 has 120 lcd outputs. the number of lcd outputs can be increased by cascading MSM6778 devices, using cascade-connected i/o pins. the bias voltage which specifies a drive level can optionally be supplied externally. the MSM6778 is suitable for various types of lcd panel. features ? logic supply voltage : 2.7 v to 5.5 v ? lcd drive voltage : a wide range from 18 v to 28 v ? applicable lcd duty : 1/100 to 1/256 ? the bias voltage can be externally supplied. ? structure: 35mm-wide tape automated bonding (tab) film (product name: MSM6778av-z-01) tin-plating ? semiconductor MSM6778 120-dot common driver (tab) e2b0031-27-y2 this version: nov. 1997 previous version: mar. 1996
2/7 ? semiconductor MSM6778 block diagram 60-bit 4-level driver 60-bit level shifter 60-bit bi-directional shift register 60-bit 4-level driver 60-bit bi-directional shift register 60-bit level shifter o 1 o 2 o 59 o 60 v dd v ee v dd v ss v dd v ss v dd v ee io 120 io 60 o 120 o 119 o 62 o 61 v eer v 5r v 2r v 1r v eel v 5l v 2l v 1l df dispoff shl io 1 cp v ddl , v ddr v ss io 61
3/7 ? semiconductor MSM6778 pin configuration (top view) input pin name pin symbol pin symbol 1 2 3 4 5 6 7 8 9 10 19 18 17 16 15 14 13 12 11 v 1l v 2l v 5l v eel v ddl shl v ss dispoff io 1 io 60 io 61 io 120 df cp v ddr v eer v 5r v 2r v 1r chip surface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ( in p ut p in side ) o 1 o 2 o 119 o 120 (lcd output side)
4/7 ? semiconductor MSM6778 absolute maximum ratings recommended operating conditions electrical characteristics dc characteristics parameter "h" input voltage "l" input voltage "h" input current "l" input current "h" output voltage "l" output voltage on resistance supply current input capacitance symbol v ih *1 v il *1 i ih *1 i il *1 v oh *2 v ol *2 r on *4 i dd *5 i ee *5 c i condition v i =v dd , v dd =5.5 v v i =0 v, v dd =5.5 v i o =C0.2 ma, v dd =2.7 v i o =0.2 ma, v dd =2.7 v v dd Cv ee =25 v, *3 i v n Cv o i =0.25 v f=1 mhz min. 0.8 v dd v dd C0.4 typ. max. 0.2 v dd 1 C1 0.4 2.0 60 400 unit v v m a m a v v k w
m a m a pf cp=28 khz, v dd =3.0 v v dd Cv ee =25 v, no load (v dd =2.7 to 5.5 v, ta= C20 to +75?c) *1 applicable to pins cp, io 1 ,io 60 ,io 61 , io 120 , shl, df, dispoff *2 applicable to pins io 1 , io 60 , io 61 , io 120 *3 v n =v 1 , v 2 , v 5 , v ee , v 2 =1/16 (v dd Cv ee ), v 5 =15/16 (v dd Cv ee ) *4 applicable to pins o 1 to o 120 *5 i dd shows the supply current between v dd and v ss . i ee shows the supply current between v dd and v ee . note: the above values are guaranteed when tcp is protected from light. note: unlike mold packages, the tape carrier package (tcp) cannot shield a light. please shield a light to secure the electrical characteristics. * v 1 >v 2 >v 5 >v ee , v dd v 1 >v 2 v dd C7v, v ee +7v v 5 >v ee v dd =v ddl =v ddr , v 1 =v 1l =v 1r , v 2 =v 2l =v 2r , v 5 =v 5l =v 5r , v ee =v eel =v eer > = > = > = parameter symbol condition range unit power supply voltage (1) v dd 2.7 to 5.5 v power supply voltage (2) v dd Cv ee * no load 14 to 28 v during liquid crystal driving 18 to 28 v operating temperature t op C20 to +75 ?c * v 1 >v 2 >v 5 >v ee , v dd v 1 >v 2 v dd C10v, v ee +10v v 5 >v ee v dd =v ddl =v ddr , v 1 =v 1l =v 1r , v 2 =v 2l =v 2r , v 5 =v 5l =v 5r , v ee =v eel =v eer > = > = > = parameter symbol condition rating unit power supply voltage (1) v dd ta=25?c C0.3 to +6.5 v power supply voltage (2) v dd Cv ee * ta=25?c 0 to 30 v input voltage v i ta=25?c C0.3 to v dd +0.3 v storage temperature t stg C30 to +85 ?c
5/7 ? semiconductor MSM6778 switching characteristics parameter symbol condition min. typ. max. unit io 1 , io 61 (io 60 , io 120 ) "h", "l" propagation delay time clock frequency cp pulse width data setup time io 1 , io 61 ? cp (io 60 , io 120 ? cp) data hold time cp ? io 1 , io 61 (cp ? io 60 , io 120 ) cp rise, fall time t plh t phl f cp t wcp t setup t hold t r (cp) t f (cp) *1 63 100 100 3 1 20 m s mhz ns ns ns ns (v dd =2.7 to 5.5 v, ta= C20 to +75?c, c l =15 pf) io 1 (io 60 ) io 61 (io 120 ) 0.8v dd 0.2v dd 0.8v dd 0.2v dd cp t wcp t f (cp) t r (cp) 0.8v dd 0.8v dd 0.2v dd 0.2v dd io 60 (io 1 ) io 120 (io 61 ) t setup t hold t plh ( t phl) t wcp *1 the relationship between t plh (t plh ) min. and t hold min. satisfies the operation in a cascade connection state. note 1: when display is controlled by dispoff pin, cp rise and fall time must be 1 m s. note 2: the above values are guaranteed when tcp is protected from light.
6/7 ? semiconductor MSM6778 functional description pin functional description ? io 1 , io 60 , io 61 , io 120 these are i/o pins of the two 60-bit bidirectional shift registers. ? shl this pin selects the shift direction of the two 60-bit bidirectional shift registers. set this pin to "h" or "l" level during power-on. shl shift direction i/o pins function l h o 1 ? o 60 o 61 ? o 120 o 60 ? o 1 o 120 ? o 61 io 1 , io 61 io 60 , io 120 io 60 , io 120 io 1 , io 61 input output input output io 1 and io 61 are data input pins for the shift register. the entered data is read in at the falling edge of a clock pulse. the data is output from io 60 and io 120 behind the number of bits (60) of the shift register. io 60 and io 120 are data input pins for the shift register. the entered data is read in at the falling edge of a clock pulse. the data is output from io 1 and io 61 behind the number of bits (60) of the shift register. ? cp this is a clock pulse input for the two 60-bit bidirectional shift registers. scan data is shifted at the falling edge of a clock pulse. ? df this is a synchronous signal input for alternate signal for lcd driving. ? dispoff this is an input used to control the output levels of o 1 to o 120 . during low level input, the v 1 level is output from the output pins o 1 to o 120 independently of the data of the shift register. see the truth table. ? o 1 to o 120 these are outputs for the 4-level drivers, which correspond directly to each bit of the shift register. one of the four levels v 1 , v 2 , v 5 , and v ee is selected and output depending on the combination of the shift register data and a df signal. see the truth table. ? v 1l , v 2l , v 5l , v eel , v 1r , v 2r , v 5r , v eer these are lcd drive bias voltage inputs. ? v ddl , v ddr , v ss these are power supply pins for the device. v dd is usually from 2.7 v to 5.5 v and v ss is 0 v.
7/7 ? semiconductor MSM6778 truth table df l l h h x shift register data l h l h x dispoff h h h h l driver output (o 1 to o 120 ) v 2 v ee v 5 v 1 v 1 x : don't care notes on use (when turning the power on or off) the lcd drivers of this ic require a high voltage. for this reason, if a high voltage is applied to the lcd drivers with the logic power supply floating, excess current flows. this may damage the ic. be sure to follow the sequence below when turning the power on or off. power on : logic circuits on ? lcd drivers on, or both on at a time power off : lcd drivers off ? logic circuits off, or both off at a time
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